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BCM8020
(R)
8-CHANNEL MULTIRATE 1.0-3.2-GBPS TRANSCEIVER
FEATURES * 8 independent transceivers supporting multiple data rates
from 1.0 Gbps to 3.2 Gbps including 1.06 Gbps, 1.25 Gbps, 2.12 Gbps, 2.488 Gbps, 2.5 Gbps, 2.667 Gbps, 3.125 Gbps, and 3.1875 Gbps Multiconfigurable to support various operating modes * Eight Independent 1.0 to 3.2-Gbps SerDes Channels * Dual quad 1.0 to 3.2-Gbps SerDes with channel alignment * SerDes-to-SerDes retimer mode: CML and XAUI interfaces * Full mesh switching maps any XAUI port to any XGMII port for full redundancy on both transmitter and receiver * Selectable TBI DDR/RTBI or XGMII parallel interface * HSTL (1.8V or 1.5V) and SSTL_2 parallel interface Low power dissipation * Less than 300 mW per transceiver channel including I/O High performance programmable Rx equalization and Tx preemphasis * Tx pre-emphasis for interoperability with CML SerDes * Rx equalization for copper interconnects Enhanced test capability * Serial and parallel loopback, BIST, 10G BERT, and random Ethernet packet generation * IEEE (1149.1) JTAG Compact 23-mm x 23-mm package with no external components required * No requirement for heat sink or airflow
SUMMARY OF BENEFITS * One device supports a variety of applications including
Gigabit Ethernet, 1x and 2x Fibre Channel, OC-48 SONET (with/without FEC), Infiniband, 10-Gigabit Ethernet, 10Gigabit Fibre Channel, or others. Flexible architecture supports programmable configurations enabling an aggregate data transfer rate of over 20 Mbps. Built-in redundancy mode provides high availability to support critical line side or backplane applications. The highspeed to high-speed retimer mode extends the use of longer traces on line card designs. Advanced 0.13- CMOS process technology provides unparalleled performance while achieving the lowest possible power consumption. Eases linecard designs to allow for multiple connectors or lowcost PCB materials such as FR4. Drive PMD devices or back-plane directly with no external clean-up circuit required. Simplifies manufacturability with integrated Built-in self-test (BIST), high-speed and low-speed loopbacks, and programmable PRBS generator/checker. Decreases complexity and reduces board space on multichannel line-card designs.
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Tx
BACKPLANE
BCM8702 Rx BCM8020 ASIC/MAC BCM8020 2x XENPAK Tx BCM8702 2x XAUI 2x XGMII/TBI 2x XGMII/TBI 2x XAUI Rx
2 Independent Quad SerDes Application Diagram
OVERVIEW
10G XAUI_0 Channel_0 (1-3.2G) Channel_1 (1-3.2G) Channel_2 (1-3.2G) Channel_3 (1-3.2G) Bus Mux 10G XAUI_1 Channel_4 (1-3.2G) Channel_5 (1-3.2G) Channel_6 (1-3.2G) Channel_7 (1-3.2G)
10G XGMII_0 Channel_0 (TBI, RTBI) Channel_1 (TBI, RTBI) Channel_2 (TBI, RTBI) Channel_3 (TBI, RTBI) (Control/Clocking)
10G XGMII_1 Channel_4 (TBI, RTBI) Channel_5 (TBI, RTBI) Channel_6 (TBI, RTBI) Channel_7 (TBI, RTBI) (Control/Clocking)
MDIO/MDC
MGMT
PBERT
Required: 1.2V, 2.5V, I/O options: 1.5V, 1.8V, 2.5V, or 3.3V
BCM8020
The BCM8020 device integrates 8 independent serializer/ deserializer (SerDes) channels leveraging Broadcom's high-performance mixedsignal design experience along with advanced 0.13- CMOS process technology. Combine this with a robust architecture offering the highest degree of flexibility and the result is a highly programmable, lowest power SerDes solution for network line-card and backplane applications. An internal switch connects the parallel and serial ports to enable fully redundant operation. The switch enables an active serial link to be switched to the parallel interface, while a protection serial link can be continuously monitored to insure its condition. In the event of failure on the active link the protection link can be instantly switched through external control to the parallel interface. On the parallel side of the device, transmitters and receivers interface with either 5-bit (RTBI) or 10-bit (TBI) wide data on each channel, or can be configured to interface to 32-bit wide data (XGMII) along with the clock and control signals. The low-speed I/O supports HSTL (1.5V or 1.8V) or SSTL_2 (2.5V) interfaces. On the serial side of the device, transmitters and receivers support serial transmissions rates ranging from 1 Gbps to 3.2 Gbps. An on-chip phase lock loop (PLL) synthesizes the supplied reference clock to support the
desired transmit rate, while vlock and data recovery (CDR) units recover the receive rate clock for timing. The interface can support singlechannel (octal) or dual-channel quad (XAUI) differential CML I/O. For high-speed serial copper connections, the device incorporates both Tx pre-emphasis on the transmit channels and Rx equalization on the receive channels. Transmit pre-emphasis is programmable to improve the overall cable reach and compensate for electrical imperfections associated with traces and connectors. Rx equalization provides optimal performance over a variety of receive interfaces. Highly programmable test capabilities exist within the device to support high-speed and low-speed loopback using generators/checkers that support PRBS 27 to 231 patterns along with IEEE802.3ae defined test patterns. A complete evaluation kit, including an evaluation board, related software, and documentation is available upon request. Applications * 1-Gigabit Ethernet and 10-Gigabit Ethernet LAN, MAN, WAN switches and routers * 1x, 2x, or 10-Gbps Fibre Channel, Infiniband, SONET network cards * Advanced Test Equipment (ATE)
Broadcom(R), the pulse logo, and Connecting everything(R) are trademarks of Broadcom Corporation and/ or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the property of their respective owners.
(R)
BROADCOM CORPORATION 16215 Alton Parkway, P.O. Box 57013 Irvine, California 92619-7013
(c) 2004 by BROADCOM CORPORATION. All rights reserved. 8020-PB04-R 04/13/04
Phone: 949-450-8700 Fax: 949-450-8710 E-mail: info@broadcom.com Web: www.broadcom.com

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